Capacitors are terrible at remembering data. But for this reason we continue doing it.

this video was sponsored by jlcpcb in a previous episode we learned about static Ram a type of memory made entirely of transistors today we are going to explore the basics of dynamic Ram a different type of memory cheaper to produce but with several challenges when implementing it hi friends my name is George and this is core dumped let's start talking about capacitors a capacitor is an electronic device that stores electric charges for example if we connect its terminals to a voltage source electricity will flow and the capacitor will begin to accumulate energy retaining it even

after being disconnected from the power source at this point the capacitor acts like a small battery capable of powering another component but only for a brief period unlike a battery that can last for hours on the other hand a mosfet is a special kind of transistor better suited for miniaturization and computer application due to its efficiency compared to other types of transistors it has three terminals the gate the source and the drain by applying a small voltage to the gate electricity can flow from the source to the drain and under certain conditions electricity can also

flow in the reverse Direction which will be important later on that being said consider this we can configure these two components in a way that uses the mosfet's gate to allow electricity to flow thus charging the capacitor once fully charged chared we can interrupt the flow of electricity and the capacitor will remain charged later to discharge the capacitor we can again use the gate to allow electricity to flow but now in the opposite direction enabling the charges to escape from the capacitor and this very simple behavior is the fundamental of dynamic Ram when the capacitor

is discharged we can consider a zero as being stored when the capacitor is charged a one is stored this circuit can be abstracted as a memory cell capable of storing one bit of information if you've watched my video on static Ram you might think that Dynamic Ram is way simpler to implement in static Ram we don't use capacitors instead we connect a series of logic gates in a clever but more complex arrangement to trap the value we want to store as an electrical signal and when I say trap I mean that the signal holds the

value even if we reset the inputs to their default States compared to this charging and discharging a capacitor look looks way easier right while a single static memory cell also known as a latch requires many transistors we only need one transistor and a very small capacitor to create a dynamic memory cell this is what makes Dynamic Ram attractive we can pack more memory cells into a given area compared to static Ram in other words we can achieve higher memory capacities using fewer components making this type of memory very cost-effective to produce but not everything is

perfect Dynamic Ram has several disadvantages consider a scenario where a dynamic memory cell is storing a one meaning the capacitor is fully charged to read the value stored in the cell our only option is to open the gate to check if electricity flows from the capacitor this means that in dynamic memory reading data is a self-destructive operation because checking whether a capacitor holds a charge involves discharging it and this is where things start to become very complicated when implementing dynamic memory for the rest of this video we're going to explore how the reliability issues of

dynamic memory are addressed a quick note for those more experienced viewers I might simplify some Concepts to keep the explanation accessible for everyone firstly is Impractical to handle each memory cell individually because that would require an insane amount of wires instead we arrange the cells in a matrix we use a single wire to connect the sources of each mosfet along each column which will refer to as bit lines and a single wire connects the gates of the mosfets along each row known as word lines as mentioned in a previous episode organizing memory cells in a

matrix allows us to locate any cell by intersecting two wires a component called a binary decoder which utilizes a series of logic gates enables us to select any given output using a decoder to select a row and another to select a column lets us pinpoint the specific intersection or memory cell we want to address this introduces the concept of a memory address however using a decoder to select a bit line isn't ideal because bit lines not only carry data into the memory cells but also out of them during a reading operation for example activating a

word line causes all cells in that row to Output their values in this scenario we cannot send signals to the outputs of a decoder because well they are outputs moreover remember that reading from a dynamic memory cell causes the capacitor to discharge since all cells in a row are connected to the same word line any charged capacitors will discharge somehow making the problem even worse when things get this complicated the solution can seem like magic until someone with patience explains it in an intuitive way my content is Free by the way hit that like button

if you want to support me now let's explain how Dynamic Ram reads values from its cells without erasing its data in the process but before a quick message from today's sponsor one thing I love about computer science is how closely Hardware relates to software more than most people think though I'm primarily a developer I also enjoy playing with electronics and I know many of you on this channel share that passion with jlcpcb you have access to multiple services that Aid both the Prototype and production stages of your projects on their website you can choose between

various Services tailored to your specific needs such as 1 to four layer pcbs 6 to 20 layers pcbs flexible pcbs PCB assembly and high Precision stainless steel stencil with high quality and competitive pricing jlcpcb is your best choice don't miss out on this opportunity to try a reliable PCB manufacturer checking the link in the description below for Simplicity let's say our Ram uses 1 volt to represent a binary one and Zer volts to represent a binary zero one thing I haven't mentioned is that if the bit lines are disconnected from the ground and then a

voltage is applied to them they act as capacitors storing charges and holding a voltage for a few NS the first step in Reading is to pre-charge the bit lines to half the working voltage of the ram in this example 0.5 volts why when we use the decoder to activate a word line we open the gate of all cells in that Row for cells holding a binary one the capacitor's voltage is greater than the bit lines so charges flow out slightly discharging the capacitor the bit line gaining some charges will see a small increase in voltage

for cells storing a binary zero the completely discharged capacitor has a lower voltage than the bit line as the gates are open charges flow from the bit line to the capacitor causing the bit line to lose some charges and its voltage to decrease these voltage changes on each bit line are detected by a component called a sense amplifier at the end of each bit line if the sense amplifier detects that the voltage is above 0 .5 Vols it outputs 1 volt representing a binary one if below 0.5 volt it outputs 0 volts representing a binary

zero the internals of these sensors are beyond the scope of this video but essentially they work by comparing two voltage sources each sensor is connected to a latch similar to those used in static Ram because the bit lines might not hold their charges long enough as soon as a sense amplifier detects a value it stores it in its latch even if the bit line discharge the sense amplifiers can still output the values read from the specified row but we don't want the value of a whole row we want the value of a specific cell in

that row here we use a component that gathers these outputs and uses the address input to determine which one is sent to the output line this is exactly what a multiplexer does internally a multiplexer of called a mux uses a decoder with a few logic gates connected in a clever way to achieve this Behavior after the sense amplifiers a multiplexer is used to ensure we can read the value stored in any memory cell we want but since reading altered the state of the capacitors storing those bits we need to reset them to their original state

this is straightforward the sense amplifier reads the value from the latch and sends it back to the bit lines restoring the capacitors to their previous state and there you have it we can read from dynamic memory without destroying our data in the process let's now turn our attention to the writing operation which Builds on the basics we've already discussed we need to apply a voltage either 0 or 1 volts to the source of the mosfet then activate the bit line to either charge or discharge the capacitor based on the desired stored value we want it

to store however there are two challenges first we aim to write to a specific memory cell not all the cells in the same row second given the existing circuitry for the read operation we can't simply bypass it our solution is to modify this circuitry since we're writing data should flow in the opposite direction thus a simple multiplexer won't work a demultiplexer or demux performs the opposite function of a multiplexer it receives a single data input and with a select input it determines which one of the outputs will receive the input value we need a component

that can act both as a multiplexer and a Dem multiplexer commonly referred to as a MX demux this component's ability to switch roles depending on whether we are reading or writing is crucial for Reliable memory operations the writing process closely resembles reading we start by charging the bit lines to 0.5 volts then activate the word line of the desired cell causing all capacitors in that row to either charge or discharge and change the voltage of the bit lines the sense amplifiers detect these changes and store the values just as they do during reading the key

difference in writing is that instead of outputting a value we input it the address tells the demultiplexer which latch to direct the input value to with only the targeted latch overwritten the sense amplifiers then send all values back through the bit lines this step ensures that each cell's capacitor either charges or discharges according to the value received in other words we write the new value while also rewriting other values in the same row to prevent data loss and this is how we write to any memory cell in The Matrix without affecting the data Integrity of

other cells in the same row here's another example where we're writing a binary zero to a different memory location the process start by charging the bit lines to then select a row the sense amplifiers detect and store the existing values the intended zero is then inputed and directed by the demultiplexer to the specific latch once the value is overwritten all values in including the newly changed one are written back to the memory cells from which they originated now before we move on to the next issue with Dynamic Ram yes we're not done yet let's outline

the steps for each operation note that except for the intermediate steps both operations appear almost identical although all of this occurs in just a few Nan there are many steps involved in reading or writing a single bit of information especially when compared to static Ram in static Ram bits are stored as electrical signals rather than charges So reading from a latch doesn't cause it to lose its value this is a significant reason why Dynamic Ram is slower than static Ram despite the process taking only Nan these extra steps slow down the entire memory addressing process

if you want to learn more about how static Ram handles this check out my previous video finally there is one more problem with Dynamic Ram that I haven't mentioned even when the gate of the mosfet is closed some small charges can still Escape moving from the drain to the source of the mosfet thus discharging the capacitor although this happens much slower than if we intentionally open the gate of the mosfet it's still a major issue if we don't address any cell in a row the information contained by those cells will be lost over time as

we are neither reading nor writing to refresh the information at the end of the operation the solution to the problem is to make this type of memory refresh itself from this point I will abstract some things to avoid over complication with everything we've learned so far understanding this operation called refreshing should be easy before the capacitors in a row have time to discharge to the point where we can no longer read their information we simply read all of the values in that row and then set the bit lines to the voltage that corresponds to those

values this ensures the cell's fully charge or discharge according to the binary value values they were originally storing essentially we are doing the same as we did for the reading and writing operations but without outputting or inputting any values so no multiplexer or Dem multiplexer is used during this process in a few words refreshing works by reading the value in a row and then write those values back to the cells they came from since the circuit has only one latch per bit line not all cells in The Matrix can be refreshed simultaneously thus each row

is refreshed one by one special circuitry is designed specifically for this purpose ideally reading and writing operations are performed when none of the rows are being refreshed but this introduces another disadvantage in Dynamic Ram each refresh cycle temporarily prevents access to the memory since the same circuitry needed for reading or writing is used for the refresh operation if the CPU attempts to read or write during a refresh cycle it must wait until the cycle is complete introducing latency the good news is that typically the intervals during which no row is being refreshed are long enough

to allow thousands of reading and writing operations before the next refresh cycle begins this is because each row generally needs to be refreshed every few milliseconds while reading and writing operations usually take nanc I'm a software engineer not an electrical engineer so I hesitate to provide exact figures for more details on aspects I don't feel fully qualified to explain such as the timing involved in Dynamic Ram operation or specific details about ddr5 Ram I highly recommend checking out these videos before getting into the final part of this video I want you to think about one

of the examples on reading or writing operation you might have noticed before that when we input an address different parts of the address are not used at the same time for example in the writing operation the part of the address that goes to the decoder is clearly used before than the part that goes to the multiplexer when the CPU sends an address to read or write to it it cannot be connected directly rather it is intercepted by another component that handle all of these timing matters knowing exactly when to let each signal reach its Target

component depending on the operation the CPU wants to perform my point here is that there is a lot of timing involved in these operations and there is some complicated circuitry that I'm not showing finally some of you might have noticed that up until now we've been working with individual bits however computers use bytes so how do we address bytes instead of bits this is quite simple part of the answer lies in the complexity of multiplexors rather than routing individual bits of information they can handle entire data buses internally this is still just a binary decoder

with a few logic gates with a more complex multiplexer we can add more columns to The Matrix and divide them into groups of eight since one bite equals eight bits in a reading operation for example the address tells the multiplexer which group of values to send to the output for writing operations a demultiplexer capable of managing buses instead of single data lines is needed in conclusion Dynamic Ram has several disadvantages over static Ram mainly because capacitors are used to store information and managing these capacitors to avoid losing information involves numerous steps that require precise timing

but even though it's slower than static Ram Dynamic Ram is cheaper to produce because it allows higher storage capacities per area hopefully this video has clarified that the cache inside your processor a type of static Ram is faster than your computer's Dynamic RAM memory modules due not only to their proximity to the CPU but also to their fundamentally different operational mechanisms so the next time you hear the term locality don't take it too literally connecting your hard drive closer to the CPU won't make it faster than your RAM and that about wraps it up for

now this video was particularly challenging to make because I had to simplify a lot of complex material without omitting essential information on how this type of memory Works remember to hit the like button if you enjoyed this video and if you want to learn more don't forget to subscribe see you in the next one